The present invention relates to a semiconductor memory device, or more particularly, to a memory architecture for a dynamic random access memory (DRAM).
DRAM integration has been progressing as rapidly as twofold every three years. This high integration of the DRAM has been made possible mainly by the progress of fine processing techniques and increases in chip size. What cannot be overlooked, however, is the fact that the memory cell structure has been improved to realize a high integration beyond the fine processing technique, as is clear when looking back on the history of the DRAM. The first memory cell structure that came on the stage had four MOS transistors required for holding a 1-bit data. After this 4-transistor cell, a 3-transistor cell appeared. Since the 16K-bit DRAM was developed, a one-transistor cell has been used.
In this way, the high integration of a memory cell structure, which had been achieved by reducing the number of elements making up the memory cell in early stages of development, has since been realized mainly by the progress of the fine processing technique and improvement in the memory cell layout in the development stages from a 16K-bit DRAM to a 1M-bit DRAM.
Since the advent of the 1M-bit DRAM, efforts have been concentrated to minimize the surface area by forming capacitances in slots formed vertically in a silicon substrate, thus reducing the size of a memory cell by a three-dimensional method beyond the fine processing technique.
The peripheral circuits such as a sense amplifier required for DRAM construction which depend on the pitches of memory cells, on the one hand, have basically remained unchanged, and have barely followed the high integration of the memory cell by the progress of the fine processing technique and the changes in layout.
Amid the constant improvement in the DRAM memory cell structure, the gap with the peripheral circuits has been widening more and more. As a result, the improvement in peripheral circuits may hold the key to determining the integrity of future DRAMs.
A construction of a conventional semiconductor memory device is shown in FIG. 1.
In FIG. 1, reference numeral 1 designates memory cells for holding 1 bit each, and numeral 2 signal wires for writing a signal into or reading it out of the memory cells 1. In the case of a DRAM, these wires are generally called bit wires. Numeral 3 designates what is generally called word wires. When one of these word wires 3 is selected by a word decoder circuit 21, the data in the memory cell 1 connected to the particular word wire 3 is produced on the bit wire 2 as a signal. Numerals 11 to 15 designate amplifiers for amplifying signals read on the bit wires 2 and connected to respective amplifiers. Numeral 20 designates a selector circuit for applying a signal from a given one of the amplifiers 11 to 15 designated by an external address to an input-output circuit 22.
Apart from this ordinary example applicable to any of DRAM, SRAM and EPROM devices, the problems of a conventional semiconductor memory device will be specifically explained with reference to a DRAM. An ordinary DRAM has a memory cell constructed as shown in FIG. 2(a), and a basic memory array as shown in FIG. 2(b) is configured. Specifically, a signal from each memory cell is applied as a differential signal to a sense amplifier SA.sub.i through a bit.sub.i wire and a bit.sub.i wire. The signal from the memory cell is thus amplified by the sense amplifier, produced on data wires D and D through a column select switch, and through an input-output circuit, outputted outside of the chip. Let C.sub.s be the capacitance of a capacitor within a memory cell and C.sub.B a stray capacitance of a bit wire. The read signal voltage .DELTA. is proportional to C.sub.S /C.sub.B as is well known. The higher the signal voltage .DELTA., the more stable the DRAM operation. For this reason, various efforts have been made to increase the value .DELTA.. C.sub.S has been decreasing with the decrease in memory cell size, and therefore C.sub.B is required to be reduced if only to lessen the decrease in .DELTA.. Specifically, it is necessary to shorten the bit wire length and reduce C.sub.B by reducing the number of memory cells connected to each sense amplifier. For this purpose, the bit wires are required to be divided into more parts if the same number of memory bits is to be secured.
Considering memory arrays shown in FIG. 3 for example, FIG. 3(a) shows an array where the number of bit wire division is one, FIG. 3(b) an array where the number of bit wire divisions is two, and FIG. 3(c) an array where the number of bit wire divisions is four. Comparison between FIGS. 3(a) to 3(c) shows that with the increase in the number of divisions, more sense amplifiers and the like are required. The resulting problems are not only a larger memory occupancy rate ##EQU1## but also the impossibility of reducing the chip size in accordance with the reduction in memory cells, indicating that the integrity could not be improved to an extent comparable to the reduction rate of memory cells.